It is advantageous to fabricate electronic circuits at the nanometer scale, because high density of circuit elements, high operating speed, and low process cost are realized. By “nanometer scale” is meant that the critical dimension of a feature is measured in nanometers. However, in nanoscale circuits, one major problem is how to fabricate nanoscale circuits efficiently.
To solve this problem, effective, low-cost methods for fabricating nanoscale circuits, employing imprinting lithography, have been developed. The imprinting process is described, for example, in U.S. Pat. No. 6,432,740, entitled “Fabrication of Molecular Electronic Circuit by Imprinting”, issued on Aug. 13, 2002, to Yong Chen, the contents of which are incorporated herein by reference.
In the imprinting process, a mold with a protruding pattern is pressed into a thin polymer film. The protruding pattern in the mold creates a recess in the thin polymer film, and thus the polymer replicates the pattern on the mold. The mold is then removed from the film. The film then is processed such that the polymer in the recess area is removed, thereby exposing the underlying substrate.
To avoid the interaction between polymer and mold, a release layer is usually coated on the mold before imprinting. The release layer is usually a self-assembled molecular layer, which can effectively reduce the interaction between the mold and the polymer. However, it is very difficult to form a defect-free coating of the release layer on the mold surface, and defects will also invariably be created during imprinting, especially when the pattern is close to 10 nm or less. These defects cause the polymer to stick to the mold.
It is also difficult to maintain a high aspect ratio between the height and width of the polymer pattern due to the mechanical properties of the polymer, and the lift-off and anisotropic etching processes become very difficult or impossible when the polymer pattern is very thin.
Thus, there is a need for a method of replicating the pattern of the mold in the metal/semiconductor layer that retains most, if not all, of the advantages of the prior art process, while overcoming the afore-mentioned problems.